As to an architecture using a scratch pad memory, a technique related to an memory-optimization is disclosed (For example, US-A 20070174829 . . . Patent reference 1). In this technique, based on a profile result of an application program, data to be used is copied from a main memory to the scratch pad memory. However, this technique disclosed in the patent reference 1 cannot be applied to the cache memory.
Furthermore, as to an architecture using the cache memory, a technique to execute the memory-optimization is disclosed (For example, U.S. Pat. No. 6,862,729 . . . Patent reference 2). In this technique, Object members of an application program to be executed are classified into a plurality of groups, and Object members belonging to the same group are located at near position on the memory. However, this technique disclosed in the patent reference 2 cannot be applied to a multi-core processor in which each core has its own memory.